In the manufacture of such chips, an important consideration is the optimum utilization of the available surface area to accommodate a maximum number of components without sacrificing operating efficiency and reliability. Thus, the cells are generally made of uniform rectangular outline disposed in parallel rows which are traversed by supply buses in the form of metallic strips insulated from the substrate by an intervening oxide layer. Each cell area is subdivided into suitably doped portions overlain by metal electrodes which, on final metallization, can be selectively connected to one another and/or to the associated supply buses.
A typical prior-art array of this character has been described in an article titled CAD PITS SEMICUSTOM CHIPS AGAINST STANDARD SLICES by Joseph H. Kroeger and Orhan N. Tozun, published 3 July 1980 in ELECTRONICS Magazine. According to this article, computer-aided design (CAD) algorithms are used to program the final metallization of the unit cells -- termed "master slices" -- of a gate array, the doping of each cell establishing therein the source, drain and channel sections of two cascades of three MOS field-effect transistors (MOSFETs) each. Within each cascade, two adjoining MOSFETS share a common source or drain section with two terminals each, disposed on opposite sides of an associated supply bus. Each cascade, therefore, consists of four such terminal (source or drain) sections separated by three channel sections of the opposite conductivity type, these channel sections being overlain by strips of polycrystalline silicon -- referred to hereinafter as polysilicon--each extending across the two supply buses and terminating at a pair of gate contacts that are associated with one transistor from each cascade and lie at opposite minor sides of the rectangular cell area. Each cell further includes an additional polysilicon strip, spaced from the MOSFET regions, that extends along a major side of the cell areas from one corner to the other and carries a pair of contacts which, however, appear unutilized in the array actually illustrated. In that array, moreover, the several rows of unit cells or master slices traversed by respective pairs of supply buses are separated from one another by relatively wide transverse zones containing further contact strips designed to enable the conductive interconnection of selected cells of one or both adjoining rows.